This course provides the solid foundations on ASIC design concepts. The course starts with the fundamentals , covers block level design from scratch, RTL coding , FSM coding techniques, Verilog design & verification constructs, Synthesis, area and timing constraints, finding critical paths in the design and optimization, Clock domain Crossing and metastability, Low Power design techniques, memories, Xilinx FPGA design etc. Exercises and interview preparation as part of this course are added advantage.
Verification has become a primary concern as all the companies want their IP to be fully verified before it goes to silicon. As a result, companies are spending more money on verification and the demand for verification engineers in the industry is growing day by day.
This course is designed to fully prepare the student to meet the verification challenges involved with medium size to complex IP’s. SystemVerilog emerged as the industry’s key verification languages as it supports coverage driven verification coupled with CRT(Constrained Random Techniques). In this course, you will learn verification concepts such as functional coverage, verification plan, layered test benches etc., and as part of SystemVerilog, OOPS concepts such as inheritance, polymorphism, encapsulation, and Constrained random techniques, coverage driven verification, virtual interfaces and callbacks etc.
UVM(Universal verification methodology) is gaining universal acceptance as the de-facto verification methodology. UVM enables efficient development and reuse of verification environments. As part of this course, you will learn all UVM concepts such as UVM factory, UVC(UVM verification components), UVM sequencers, configuration database, sequence libraries, TLM, virtual sequencer, register abstraction, callbacks etc.